NIELIT To Fill 83 Vacancies Of Teaching Posts, Consultant, Engineer And Other Posts 2025

The National Institute of Electronics and Information Technology, Dwarka, New Delhi has issued Advertisement No. NHQ‑12/22/2025‑NC (3160304) for one‑year contractual engagement of 83 teaching, technical and consultancy positions. The posts span Professor, Associate Professor, Assistant Professor, VLSI design roles, DevOps, Full Stack development, graphics design and project support.

As per the advertisement dated 14 July 2025 the maximum age for most positions is 50 years, with technical roles ranging between 40 and 45 years. Consolidated monthly pay ranges from ₹40,000 for Junior VLSI Engineers and Graphics Designer to ₹2.50 lakh for the specialised Consultant (Design Verification & EDA Integration). Selection will be through document screening followed by interview; some roles include skill tests or interaction meetings.

Eligible candidates must submit the prescribed offline application form, fee proof and self‑attested documents to the Registrar, NIELIT Bhawan, Sector‑8, Dwarka, New Delhi 110077 on or before 25 July 2025. A non‑refundable registration fee of ₹500 per position is payable online to the Bank of India account specified in the notice.

Important Dates: Notification issued on 14 July 2025, applications accepted from the same date, last date for receipt of offline forms 25 July 2025 up to working hours.

Vacancy Details: The recruitment includes the following positions:

Assistant Professor – 28 Posts
Associate Professor – 13 Posts
Professor – 6 Posts
Team Lead (VLSI Design) – 5 Posts
VLSI Design Expert / Junior VLSI Engineer – 10 Posts
Senior Trainers (VLSI Design) – 4 Posts
Team Leader (Platform Development) – 1 Post
DevOps Engineer – 4 Posts
Full Stack Engineer – 6 Posts
Graphics Designer – 1 Post
Sr. Resource Person – 1 Post
Consultant (Design Verification & EDA Integration) – 1 Post
Senior Resource Person (Project Officer) – 1 Post
Resource Person – 1 Post
Consultant – 1 Post

Eligibility Criteria:
Teaching posts require B.E/B.Tech and M.E/M.Tech or integrated M.Tech with first class in the relevant branch, or B.E/B.Tech with Ph.D. Associate and Professor grades demand research publications and post‑Ph.D experience as detailed in the advertisement. Technical positions call for degrees in Electronics, Computer Science, VLSI, IT or related areas with specified industry or R&D experience. The Consultant (EDA Integration) needs at least eight years’ ASIC/FPGA design verification experience plus strong SystemVerilog/UVM skills. All applicants must meet the age limits stated for their respective roles.

How to Apply:
Candidates should download the appropriate form from the NIELIT recruitments page, fill it clearly, attach proofs, include the online fee receipt and dispatch the complete set to the Registrar at NIELIT HQ Dwarka so it reaches by 25 July 2025.

Application Fee:
A registration fee of ₹500 per post is payable through online transfer to the NIELIT Bank of India account given in the advertisement; print the transaction details to enclose with the form.

Selection Process:
Applicants will be screened on the basis of submitted documents. Short‑listed candidates will undergo document verification and interview. Certain posts such as Junior VLSI Engineer or Graphics Designer may additionally involve skill tests or interaction meetings before final empanelment.

NIELIT Official Notification:
Candidates must read the detailed advertisement dated 14 July 2025 for complete eligibility, reservation, tenure, pay details and list of required documents before applying offline.
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